7-1 rev b pasic 3 fpga tm family high performance and high density with low cost and complete flexibiltiy pasic 3 fpga family device highlights high performance & high density densities up to 60,000 usable pld gates with 316 i/os fastest fpga family available at any density level 16-bit counter speeds over 300 mhz, data path speeds over 400 mhz e asy to u se / fast development cycles abundant interconnect makes devices 100% routable with pin-outs locked variable-grain logic cell provides high performance and 100% logic utilization comprehensive design tools include fast, efficient ver- ilog/vhdl synthesis low cost 0.35m four-layer metal non-volatile cmos process small die sizes - first fpga family to use staggered pads advanced i/o capabilities multi-volt compatible i/os for 3.3 volt and 5 volt system interfaces pci compatibility with 3.3v and 5.0v buses full jtag boundary scan registered i/o cells with individually controlled clocks and output enables table 1. pasic 3 device family d evice h ighlights QL3004 ql3012 ql3025 ql3040 ql3060 usable pld gates 4,000 12,000 25,000 40,000 60,000 logic cells 96 320 672 1,008 1,584 maximum flip-flops 218 598 1,212 1,764 2,692 maximum i/os 74 118 204 252 316 packages plcc 68, 84 84 tqfp 100 100,144 144 pqfp 208 208 208 pbga 256 456 456
2 preliminary 7-2 pasic 3 fpga tm family family summary the pasic 3 family is fabricated on a 0.35mm 4- layer metal process using quicklogic?s patented vialink ? technology to provide a unique combination of high performance, high density, low cost, and complete flexibility. the five devices in the family range from 4,000 usable pld gates with 82 i/os to 60,000 usable pld gates with 3163 i/os, making them among the largest fpgas available. while other fpga families sacrifice performance to reach these densities, the pasic 3 family is the fastest available from any vendor at any density level - with 16-bit counter speeds that exceed 300 mhz and datapath speeds over 400 mhz. with die sizes as small as half those of competing fpgas, pasic 3 devices provide high levels of den- sity and performance at a lower cost. the pasic 3 family also provides 100% routability, even with all logic cells used and i/o pins fixed. this capability is critical for larger designs completed using high-level hardware description languages such as verilog and vhdl. devices in the pasic 3 family are based on an array of highly flexible logic cells which have been opti- mized to efficiently implement a wide range of logic functions at high speed. each cell can implement one large function, five independent smaller func- tions, or any combination in-between. logic cells are configured and interconnected by rows and columns of routing metal and vialink metal-to-metal antifuses. because vialink antifuses are small, fast, and are placed between metal layers above the logic cells (rather than on the silicon sub- strate), they can be located at every routing track junction. this approach allows abundant intercon- nect resources with small die sizes. pasic 3 family members feature 3.3 volt operation with multi-volt compatible i/os. thus the devices can easily operate in 3 volt only systems, as well as mixed 3.3 volt/5 volt systems. a wide range of additional family features comple- ments the pasic 3 family. all members include 5 volt and 3 volt pci-compliant speed grades capable of implementing bus master and target applications at 33 mhz with zero wait states. i/o pins provide individually-controlled output enables, dedicated input/feedback registers, and full jtag capability for boundary scan and test. different family members in the same package are pin-compatible with one another, permitting easy design migration within the family. in addition, pasic 3 devices provide the ben- efits of non-volatility, high design security, immediate functionality on power-up, and self-contained single chip solutions. software support for the pasic 3 family is available through three basic packages. the turnkey pc-based quickworks ? package, shown in figure 1, provides the most complete fpga software solution from design entry, to logic synthesis, to place and route, to simulation. quickworks includes vhdl, verilog, schematic, boolean, and mixed-mode entry with fast and efficient logic synthesis provided by the inte- grated synplicity synplify lite ? tool, specially tuned to take advantage of the pasic 3 architecture. quickworks also provides functional and timing sim- ulation for guaranteed timing and source-level debug- ging. figure 1. quickworks tool suite the pc/sun/hp-based quicktools ? and pc-based quickworks ? -lite packages are a subset of quick- works and provide a solution for designers who use cadence, mentor, synopsys, viewlogic, intergraph, or other third-party tools for design entry, synthesis, f amily s ummary d evelopment t ools 6lpxodwr u verilog schematic 4xlfn 7rrov 3odfh5rxw h $qdo\] h mi xed mode vhdl quickboolea n 7klug3duw\ 'hvljq (qwu \ 6\qwkhvlv 7klug3duw\ 6lpxodwlrq +' / 6hqvlwlyh (glwru 6fkhpdwlf &dswxu h 6\qsolflw \ 6\qwkhvlv
7-3 pasic 3 fpga tm family or simulation. quicktools and quickworks-lite read edif netlists and provide optimization, place and route, timing analysis, and back-annotation support for all quicklogic devices. quicktools and quick- works-lite also write out ovi, vital, vss, edif, lmc, sdf, and viewsim files to support a wide range of third-party modeling and simulation tools. logic cell and ram module organization the pasic 3 family contains devices covering a wide spectrum of density requirements. the five mem- bers range from 96 logic cells to 1,584 logic cells arranged in regular two-dimensional arrays. horizon- tal and vertical routing channels containing up to thirty wires run above the logic cells to connect func- tions. each logic cell includes one pre-configured register, plus the logic to implement an additional indepen- dent latch. therefore, users have up to three fully independent flip-flops for every two logic cells. since each input and i/o cell also include a register, the total number of available flip-flops in a device equals the number of logic cells multiplied by 1.5 plus the total number of i/o pins. for example, the ql3025 has: (672 logic cells x 1.5) + (204 i/o cells) = 1212 available flip-flops. .vialink ? programming element programmable devices implement customer-defined logic functions by interconnecting user-configurable logic cells through a variety of semiconductor switch- ing elements. the maximum speed of operation is determined by the effective impedance of the switch in both programmed on, and unprogrammed off states. in pasic 3 devices the switch is called a vialink ele- ment. the vialink element is an antifuse formed in a via between the metal three and metal four layers of a four-layer metal cmos process. the direct metal-to- metal link, created as a result of programming, achieves a connection with resistance values below 50 ohms. this is less than 5 percent of the resistance of an eprom or sram switch and 10 percent of that of a dielectric antifuse. the capacitance of an unprogrammed vialink site is also lower than these alternative approaches. the resulting low rc time constant provides speeds up to two times faster than older generation technologies. figure 2 shows a programmed vialink site. in a cus- tom metal-masked asic, such as a gate array, the top and bottom layers of metal make direct contact through a tungsten-plug via. in a vialink-program- mable asic device the two layers of metal are ini- tially separated by an insulating amorphous silicon layer with resistance in excess of 1 gigaohm. a programming voltage applied across the via forms a bidirectional conductive link connecting the second and third metal layers, as shown in the microphoto- graph of the vialink element in the figure above. figure 2. vialink ? element l ogic c ell and ram m odule o rganization v ia l ink p rogramming e lement { { vialink ? amorphous silicon antifuse metal 4 tungsten plug metal 3
4 preliminary 7-4 pasic 3 fpga tm family four layer metal cmos process quicklogic pasic 3 devices are fabricated on a conventional high-volume cmos process. the base technology is a 0.35 micron, n-well cmos technology with a single polysilicon layer and four layers of metal interconnect as shown in figure 3. the only deviation from the standard process flow occurs when a single mask is used for the amorphous silicon to form the vialink elements between the metal deposition steps. figure 3. four layer metal vialink ? structure as the size of a vialink ? via is identical to that of a standard metal interconnect via, programmable ele- ments can be packed very densely. the packing den- sity is limited only by the minimum dimensions of the metal-line to metal-line pitch. as a result, pasic 3 devices typically have four to six times the number of programmable elements per usable logic gate, with smaller die sizes, than do sram-based fpgas. fur- thermore, the vialink technology can easily scale to smaller process geometries in the future. array of logic cells the pasic 3 device architecture consists of an array of user-configurable logic building blocks, called logic cells, set beneath a grid of metal wiring channels sim- ilar to those of a gate array. through vialink ele- ments located at the wire intersections, the output(s) of any cell may be programmed to connect to the input(s) of any other cell. by moving all interconnect resources above the logic cells, die sizes are less than half of two-layer metal technologies, as shown in fig- ure 4. the regular and orthogonal interconnect makes the pasic 3 architecture similar in structure and perfor- mance to a metal-masked gate array. it also ensures that system operating speed is far less sensitive to partitioning and placement decisions, as minor revi- sions to a logic design can easily be incorporated without re-routing problems, resulting in only small changes in performance. adequate wiring resources permit 100% automatic placement and routing of designs using up to 100% of the logic cells and i/o pins. this capability has been demonstrated on designs that also include a high percentage of fixed pin placements. the pasic 3 logic cell, shown in figure 5, is a gen- eral-purpose building block that can implement most ttl and gate array macro library functions. it is equivalent to the pasic 2 cell, allowing easy design upgrades. the cell has been optimized to maintain the inherent speed advantage of the vialink technol- ogy while ensuring maximum logic flexibility. since the logic cell has multiple outputs, it can implement one large function or multiple smaller independent functions in parallel. the function of a logic cell is determined by the logic levels applied to the inputs of the and gates and multiplexers. vialink sites located on signal wires tied to the gate inputs perform the dual role of configur- ing the logic function of a cell and establishing con- nections between cells. f our l ayer m etal cmos p rocess metal 3 horiz. tracks metal 4 vert. tracks logic cell wiring vialink ? amorphous silicon antifuse tungsten plug via a rray of l ogic c ells
7-5 pasic 3 fpga tm family figure 4. 4-layer metal reduces die sizes the complete pasic 3 logic cell consists of two 6- input and gates, four two-input and gates, six two- to-one multiplexers and one d flip-flop with asynchronous set and reset controls. the cell has a fan-in of 29 (including register control lines) and fits a wide range of functions with up to 16 simultaneous inputs. the high logic capacity and fan-in of the logic cell accommodate many user functions with a single level of logic delay (resulting in high performance) while other architectures require two or more levels of delay. examples of functions which can be implemented with a single logic cell delay include: one 16-input and gate, two 6-input and gates plus two 4-input and gates, two 6-input and gates plus two 2:1 or one one 4:1 multiplexer, one 5-input xor gate, one 3-input xor and one 2-input xor, and numerous sum-of-products functions with up to 16 inputs or 16 product terms. the d-type flip-flop can also be configured to provide j-k, s-r, or t-type functions. two independent set and reset inputs can asynchronously control the output condition. additional flip-flops can be built using the multiplexers in the logic cell. in general, up to three independent flip-flops are available for every two logic cells. the combination of wide gating capability, a built-in register, and the capability to build additional registers makes the logic cell particularly well suited to the design of high-speed state machines, shift registers, encoders, decoders, arbitration and arithmetic logic, as well as a wide variety of counters. figure 6 shows some of the possible configurations of the logic cell. since all connections within the cell are hard-wired, the various functions are available in parallel. thus very wide, complex functions are implemented with the same cell speed (about 2ns) as the much smaller "fragment" functions. related and unrelated functions can be packed into the same logic cell, increasing effective density and gate utilization. figure 5. logic cell figure 6. efficiency and high performance 2-layer metal 4-layer metal qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 np e2 d2 ns f1 f3 f5 f6 f2 f4 qc qr mp az oz qz nz fz
6 preliminary 7-6 pasic 3 fpga tm family this level of flexibility is especially important for designs synthesized from hdls such as vhdl or verilog. typically, synthesis tools prefer "gate array- like" fine-grained architectures; however, fine-grained fpga architectures generally yield very poor perfor- mance due to the long delays resulting from building functions with multiple levels of gates and slow inter- connect elements. the pasic 3 family gives logic synthesis tools the needed degrees of freedom for the high logic utilization benefits of a fine-grained archi- tecture without sacrificing the high performance ben- efits of a large-grained, high fan-in architecture. the pasic 3 macro library contains more than 400 of the most frequently used logic functions optimized to fit the logic cell architecture. a detailed under- standing of the logic cell is therefore not necessary to design successfully with pasic 3 devices. cae tools will automatically map a conventional logic schematic or hdl file into a device and provide excellent per- formance and utilization. i/o features the pasic 3 family features three distinct types of pins to maximize performance, functionality and flex- ibility: bidirectional i/o pins, input-only pins, and jtag pins. bidirectional pins can be programmed for input, out- put, or bidirectional operation. as shown in figure 7, each bidirectional i/o pin is associated with an i/o cell which features a two-input or gate, a three-state output buffer, an input buffer, and an input/feedback register. the or gate allows active high or active low outputs, or can be used for high-speed logical or functions independently of internal logic cells. the three-state buffer fed by the or gate allows the i/o pin to act as an input or output. the buffer ? s output enable can be individually controlled through the logic cell array or any pin, or bank-controlled through one of two global networks. figure 7. i/o cell for output functions, i/o pins can be individually configured for active high, active low, or open- drain inverting operation. in the active high and active low modes, the pins of higher speed grade devices are fully pci-drive compliant. in addition, all i/os are designed to ensure quiet switching charac- teristics while maintaining high speed. for input functions, i/o pins can provide combinato- rial or registered data back to the logic array. for registered input operation, i/o pins drive the d input of i/o cell registers, allowing data to be captured with fast set-up times without consuming internal logic cell resources. when i/o pins are unused, the oe controls can be permanently enabled, allowing the i/o cell registers to be used for registered feed- back into the logic array. i/o cell registers are con- trolled by clock, clock enable, and reset signals, which can come from the logic array, any pin, or from one of the two global networks. i/o f eatures
7-7 pasic 3 fpga tm family figure 8. basic input cell figure 9. input cell with network driver input-only pins are special low-skew, high-drive-cur- rent pins for driving high fan-out nets. as shown in figure 10a, each input-only pin is associated with an input cell which can provide true or complement combinatorial or true registered signals to the device. figure 10b shows that a subset of the input-only pins can also drive one of two types of special highly-dis- tributed, buffered networks typically used for routing clock or control signals. these networks are described in detail in the following routing resources section of this data sheet. jtag pins support ieee standard 1149.1a to pro- vide boundary scan capability for pasic 3 devices. boundary scan can be used to test pin connections and to view the state of internal nodes. test data and commands are serially shifted into the device, then results are serially shifted out and examined. the fol- lowing public instructions are supported: bypass, extest, and sample/preload. six pins are dedicated to jtag and programming functions on each pasic 3 device, and are unavail- able for general design input and output signals. tdi and tdo are jtag test data input and output, shifted by control clock tck. tms is jtag test mode select and trstb is jtag test reset input. most of the five jtag pins also have separate func- tions used only during device programming. a sixth pin, stm, is used only for programming . routing resources five types of routing resources are provided in pasic 3 devices: segmented wires, dual wires, express wires, quad wires, and distributed networks. seg- mented wires run vertically throughout the routing array and dual wires run horizontally. segmented and dual wires are predominantly used for local con- nections. they effectively traverse one or two logic cells and then use a vialink element to continue to the next cell or to change direction. their low resis- tance and capacitance provide high performance for local logic cell connections. express lines run the length of the device uninter- rupted. these lines have a higher capacitance than segmented wires, but provide higher performance for long routes or high fan-out nets. quad wires are similar to segmented wires in that they are used for local interconnect, but instead of having vialink elements at each logic cell, they have vialink elements every fourth logic cell. as a result, these wires are typically used to implement interme- diate length or medium fan-out nets. distributed networks are highly buffered, well distrib- uted routing structures designed to provide low-skew signals for high fan-out nets. one type, called the "array" network, routes array logic cell flip-flop clock, set, and reset signals. the second type, called the "global" network, routes array logic cell flip-flop con- trols, input and i/o register controls, i/o cell output enable controls, and the f1 logic cell input. array networks can only be driven by specific input-only pins. global networks can be driven by specific input-only pins, or by any other pin or any logic cell output. routing wires are contained within horizontal and vertical channels running above logic cells within the logic cell array. by programming the appropriate vialink elements, any logic cell output can be con- nected to any other logic cell input. quicklogic ? s four-layer metal vialink process provides abundant wire and programming resources, allowing 100% routability and pin-out maintainability with no manual routing. the place and route software not only auto- matically routes the design, but automatically allo- cates signals to the appropriate types of wires (based d e r q to logic array d e r q to logic array to array or global network r outing r esources r outing r esources
8 preliminary 7-8 pasic 3 fpga tm family on design constraints and connectivity) to ensure the optimum speed/density combination. the pasic 3 family is based on a 0.35 micron high- volume cmos fabrication process with the vialink programmable-via antifuse technology inserted between the metal deposition steps. the vialink ele- ment exists in one of two states: a highly resistive unprogrammed off state and the low impedance, programmed on state. programmed vialink ele- ments connect the outputs of one logic cell to the inputs of other logic cells directly or in combination with other links. an unprogrammed link experiences a worst case voltage equal to vcc biased across its terminals. a programmed link carries a.c. current caused by charging and discharging of device and interconnect capacitances during switching. no d.c. current flows through either a programmed or an unprogrammed link during operation as a logic device. studies of test structures and complete pasic devices have shown that an unprogrammed link under vcc bias remains in the unprogrammed state over time. similar tests on programmed links under current bias exhibit the same stability. these tests indicate that the long term reliability of the combined cmos and vialink structure is similar to that of the base cmos process. for further details, contact quicklogic. propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. the ac characteristics in each individual device data sheet are a design guide to provide initial timing estimates at nominal condi- tions. worst case estimates are obtained when nomi- nal propagation delays are multiplied by the appropriate delay factor, k, as specified in the delay factor table (operating range). the quickworks- lite/quicktools/quickworks software incorporates data sheet ac characteristics into the design data- base for pre-place-and-route timing analysis. the spde delay modeler extracts specific timing parame- ters for precise path analysis or simulation results fol- lowing place and route. the following diagrams provide timing models for several of the most common paths in the devices. these models can be used with the "k factor" and "ac characteristics" information (in the individual device data sheets) to estimate timing.
7-9 pasic 3 fpga tm family figure 10. sequential timing with array clock figure 11. sequential timing with global clock i/clk i/o i/o tack tclk toutlh touthl ti/o logic cell pin-to-pin calculations clock to out: tack + tclk + (toutlh or touthl) setup time : (ti/o + tsu) - tack tsu i/clk i/o i/o tgckp tclk toutlh touthl ti/o logic cell pin-to-pin calculations clock to out: tgckp + tgckb + tclk + (toutlh or touthl) setup time : (ti/o + tsu) - (tgckp + gckb) tsu tgckb
10 preliminary 7-10 pasic 3 fpga tm family figure 12. sequential timing for i/o and input cells figure 13. combinatorial path timing i/clk i/o tgckp tclk or ticlk toutlh touthl tisu i/o cell or input-only cell pin to pin calculations clock to out: tgckp + tgckb + (tclk or ticlk) + (toutlh or touthl) setup time : tisu - (tgckp + gckb) i/o tgckb i/o i/o i/o ti/o lo g ic cell pin-to-pin calculations input to output: ti/o + tpd + (toutlh or touthl) tpd toutlh touthl
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